The starts of programmable logic are at the end of the ’70s. They emmerged because the complexity of PCB were increasing and the engineers needed tools to develop different interconnection and glue logic to several projects.
There are two or three all mighty companies in programmable logic. For me, and its subjective are, Altera, Xilinx and Actel.
CPLDs (Compact Programmable Logic Devices) started first (obviously before that were SPLD). They were easy to configure, have high bus rates at faster speed sucha as 5ns.
- Ease of design: you can write an HDL (Hardware Description Logic) file and modify for expand the bus.
- Board Area Reduction: Because of their size i.e. PLCC, they could fit well in non intrusive space and implement a lot of hardware inside.
- Reduce costs: you are implementing hardware inside… multipliers, adders, decoders; so you can compare how many chips you have saved not to purchase and make a cost effective design.
This photo above is about a Xilinx CPLD and a first programmable starter board using JTAG interface via parallel port.
Of course, there are more advanced topics like FPGAs, but let’s make it easy right now. Down is a image view of the Spartan 3E Starter Board.
But how do you code a CPLD?. Well you have to develop source code in VHDL (Very High Speed Integrated Circuits Hardware Description Language) format. In example, if i want to describe a simple AND gate in HDL i will code this:
ENTITY And2 IS — A definir entidad
PORT ( — Puertos a definir
A : IN STD_LOGIC; — Entrada 1 de la compuerta
B : IN STD_LOGIC; — Entrada 2 de la compuerta
Y : OUT STD_LOGIC — Resultado de la compuerta
); — Fin de la definición de E/S
END AndN; — Fin de la entidad
ARCHITECTURE Bhvl OF And2 IS — Inicio de la arquitectura
BEGIN — Inicio de descripcion
Y <= A AND B; — Resultado de la compuerta
END Bhvl; — Fin del comportamiento
It implementation is called behavioural, because we describe the behaviour of the interface.
Next, for testing, you will have to construct a simulation file for verify your code. This, when testing, will look something like (this is not the test of the AND vhld file):
Well, that’s good, but, how i designate the pin that i will use?. That’s a good question!. The program that you will use, in case Xilinx ISE. The description of the I/O will be:
NET “A” LOC = P38;NET “B” LOC = P39;NET “Y” LOC = P40;
- Arithmetic: Arithmetic Unit, Full Adder, Half Adder, etc.
- Combinational Gates: And, OR, Comparator, XOR, XNOR, NOT
- Counter: Binary, Ring, Timer
- Decoders: BCD to 7-Seg, Decoders, Demux
- Priority Encoder
- Finite State Machines: Mealy and Moore state machines
- Majority Vote
- ALU: It mixes cominational and arithmetic to make it. Here is the ALU Schematic.
- Sequential circuits: Flip Flops and Latchs
- Multiplexers: 2-1, 4-1, 8-4
- 00 to 99 Counter